cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 1/8 MTP4411M3 cystek product specification -30v p-channel enhancement mode mosfet MTP4411M3 bv dss -30v i d -5a 40m (typ.) r dson @v gs =-10v, i d =-4a r dson @v gs =-4.5v, i d =-3a 58m (typ.) features ? single drive requirement ? ultra high speed switching ? pb-free lead plating package symbol outline absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds -30 v gate-source voltage v gs 20 v continuous drain current @ t a =25 c i d -5 a continuous drain current @ t a =70 c i d -4 a pulsed drain current i dm -20 *1, 3 a total power dissipation (t a =25 ) pd 1.5 *2 w linear derating factor 0.01 w/ c operating junction and storage temperature tj, tstg -55~+150 c note : *1 . pulse width limited by maximum junction temperature *2. surface mounted on 1 in 2 copper pad of fr-4 board; 250 c/w when mounted on min. copper pad *3. pulse width 300 s, duty cycle 2% MTP4411M3 sot-89 d g d s g gate s source d drain
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 2/8 MTP4411M3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 17 c/w thermal resistance, junction-to-ambient, max r th,j-a 83.3 (note) c/w note : when mounted on a 1 in 2 pad of 2 oz. copper; 250 c/w when mounted on min. copper pad electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss -30 - - v v gs =0, i d =-250 a v gs(th) -1 -1.4 -2.5 v v ds =v gs , i d =-250 a g fs - 5 - s v ds =-10v, i d =-4a i gss - - 100 na v gs = 20v, v ds =0 - - -1 a v ds =-24v, v gs =0 i dss - - -10 a v ds =-20v, v gs =0 (tj=125 c) - 40 45 i d =-4a, v gs =-10v *r ds(on) - 58 75 m i d =-3a, v gs =-4.5v dynamic ciss - 796 - coss - 88 - crss - 71 - pf v ds =-15v, v gs =0, f=1mhz *t d(on) - 6 - *t r - 10 - *t d(off) - 18 - *t f - 5 - ns v ds =-15v, i d =-1a, v gs =-10v, r g =6 *qg - 11 - *qgs - 2 - *qgd - 3 - nc v ds =-15v, i d =-4a, v gs =-10v source-drain diode *i s - - -2.3 *i sm - - -9.2 a *v sd - -0.76 -1.2 v v gs =0v, i s =-1a *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping marking MTP4411M3 sot-89 (pb-free lead plating package) 1000 pcs / tape & reel 4411
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 3/8 MTP4411M3 cystek product specification typical characteristics typical output characteristics 0 10 20 30 40 50 60 70 80 024681 -v ds , drain-source voltage(v) -i d , drain current (a) 0 -v gs =2v --v gs =4v -v gs =3v -v gs =10 v -v gs =9v -v gs =5v -v gs =6v -v gs =7 v -v gs =8v brekdown voltage vs ambient temperature 28 30 32 34 36 38 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -bv dss , drain-source breakdown voltage (v) i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.001 0.01 0.1 1 10 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =-10v v gs =-4.5v v gs =-2.5v v gs =-3v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 -i dr , reverse drain current (a) -v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 024681 gate-source voltage-vgs(v) r ds( on) , static drain-source on- state resistance(m) 0 i d =-4a drain-source on-state resistance vs junction tempearture 20 30 40 50 60 70 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , static drain-source on-state resistance(m) v gs =-10v, i d =-4a
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 4/8 MTP4411M3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss normalized threshold voltage vs junction tempearture 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) -v gs( th) ,normalized threshold voltage i d =-250 a forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 -i d , drain current(a) g fs , forward transfer admittance-(s) v ds =-10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 02468101214 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-15v i d =-4a maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) dc 10ms 100ms 1ms 100 s t a =25c, tj=150c v gs =-10v, r ja =83.3c/w single pulse r ds( on) limite 10 s 1 s maximum drain current vs junctiontemperature 0 1 2 3 4 5 6 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =-10v
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 5/8 MTP4411M3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 10 20 30 40 50 60 70 02468 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =10v transient thermal response curves 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r ja (t) 4.r ja =83.3c/w
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 6/8 MTP4411M3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 7/8 MTP4411M3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) 217 c ? time (t l ) 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c400m3 issued date : 2011.10.06 revised date : 2013.08.07 page no. : 8/8 MTP4411M3 cystek product specification sot-89 dimension inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1732 0.1811 4.40 4.60 f 0.0591 typ 1.50 typ b 0.1551 0.1673 3.94 4.25 g 0.1181 typ 3.00 typ c 0.0610 ref 1.55 ref h 0.0551 0.0630 1.40 1.60 d 0.0906 0.1024 marking: 4411 e f g c b a i d h 3 2 1 3-lead sot-89 plastic surface mounted package cystek package code: m3 style: pin 1. gate 2. drain 3. source device name date code 2.30 2.60 i 0.0138 0.0173 0.35 0.44 e 0.0126 0.0205 0.32 0.52 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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